1. Field of the Invention
The present invention relates to a memory control apparatus for controlling a memory access command to be used and a memory control method.
2. Description of the Related Art
As the main memory of a computer system, a synchronous DRAM is used in general. Along with the improvement of functionality and performance of computer systems, requirements for the access performance of the synchronous DRAM are growing. To make the most of the performance, various methods for controlling access to the synchronous DRAM have been proposed concerning a memory control apparatus.
When independently controlling memory access to a plurality of banks of a synchronous DRAM, the issuance timings of a plurality of commands overlap in some cases. Since the specifications of the synchronous DRAM do not permit issuance of the plurality of commands at the same timing, the issuance of any one of the commands needs to be delayed.
In Japanese Patent Laid-Open No. 2007-249837, the column address of the current memory transfer is compared with the column address of the next memory transfer. If the column addresses are different, a READ A command (READ command with precharge) or a WRITE A command (WRITE command with precharge) is issued. On the other hand, if the column addresses are identical, READ commands or WRITE commands of the same column address are continuously issued.
According to the method disclosed in Japanese Patent Laid-Open No. 2007-249837, however, the column address of the current memory transfer is compared with the column address of the next memory transfer but not with the memory transfer address after next. Hence, if transfer of the same column address exists after next the transfer for issuing a command, a READ A command or a WRITE A command is used. In this case, if the next transfer is done for a different bank, access can be performed without precharge. Hence, unnecessary precharge occurs, and the transfer efficiency lowers.